Many digital systems consist of multiple processing subsystems (e.g., modules) that are each controlled by a different clock source. These clock sources may be unsynchronized, meaning that they produce clock signals that are mismatched with one another in terms of phase and/or frequency.
Having unsynchronized clocks in a digital system can cause problems when data is transferred between subsystems. For example, in some digital systems, data samples are passed between subsystems in frames. A frame consists of a predefined number of samples, wherein each sample has one or more bits. In these types of systems, a receiving subsystem typically buffers (i.e., temporarily stores) a sequence of incoming samples from a transmitting subsystem until the receiving subsystem determines that a complete frame has been received. If the transmitting and receiving subsystems are controlled by unsynchronized clocks, eventually the frame timing may be off, and sooner or later the receiving subsystem may receive too many or too few samples per frame. Receiving too few samples per frame is referred to as buffer underflow, and receiving too many samples per frame is referred to as buffer overflow. The buffer overflow/underflow caused by clock mismatch is also referred to as “sample slipping”.
A known solution to sample slipping involves discarding extra samples from a buffer when it overflows and stuffing repeated samples in the buffer when it underflows. An illustration of this approach is shown in FIG. 1. In this example, a frame includes n samples. With unsynchronized subsystems, when a transmitter's clock is faster than a receiver's clock, the buffer 10 overflows with too many samples. To remedy this, the extra samples in the overflowing buffer 10 are removed. In this case, there is one extra sample, so the n+1 sample, or last sample, is discarded. When the transmitter's clock is slower than the receiver's clock, the buffer underflows with too few samples. To fill the underflowing buffer 12, some of the received samples are simply repeated and added to the underflowing buffer 12. In this example, the missing nth sample is filled by repeating the n−1 sample as the nth sample.
The above-described solution to sample slipping, however, introduces discontinuity in the samples due to abrupt addition or deletion of samples. In certain digital systems, such as audio and/or visual processing systems, this discontinuity can introduce undesirable, perceptible artifacts into the output of the digital system. Thus, there is a need for an improved sample slipping solution that reduces undesirable artifacts, thereby improving the performance of digital systems having unsynchronized clocks.